This relates generally to integrated circuits in the interfacing of electronic systems and devices with one another, and more particularly to interface circuits for receiving power from and providing power to connected devices.
The interface of various electronic systems has become much more standardized in recent years with the widespread implementation of cables, connectors, and controllers according to the various Universal Serial Bus (USB) standards. A wide range of modern devices and systems, particularly those intended for consumer and office use, can now readily interface with one another over USB interfaces to communicate data and, in some instances, to allow one USB device to power another. Indeed, USB is used in charging the battery of many modern smartphones, either from a wall charger or from a host device (e.g., a desktop or laptop computer).
USB Type-C (or “USB-C”) interfaces have been developed that offer many improvements over conventional USB interfaces (e.g., USB 1.0, USB 2.0), such improvements including reversible cables, “flippable” plugs (i.e., plugs that can be inserted in either orientation), and higher levels of power delivery, while maintaining backward-compatibility with USB 2.0 data communications. USB Type C interfaces allow a given port to function as a “downstream-facing port” (DFP), as at a host device, or as an “upstream-facing port” (UFP), as at an accessory device. In contrast to conventional USB connectors in which the shape of the plug identifies which device is the host and which is the accessory, two “channel configuration” (“CC”) pins of the USB Type-C connectors electrically establish the host-accessory relationship for data and control communication. More specifically, host devices have pull-up resistors coupled to the CC pins while accessory devices have pull-down resistors coupled to those pins; monitoring of the voltage at these CC pins allows a device to detect connection to another device, and also the host-accessory relationship of that connection. USB Type-C also defines “dual-role ports” (DRPs) that can serve as either a DFP or a UFP, depending on the role of a device to which it is connected. Identification of the direction of a DRP is performed by the device alternately identifying as a DFP and then a UFP until a stable state is reached. Some DRPs have a preferential DFP or UFP state to facilitate negotiation in the connection of two DRPs to one another.
The USB Type-C standard provides the potential for a single charger to safely and rapidly charge a number of different devices, including laptops, smartphones, tablets, cameras, and any number of other functions. For example, under a power delivery option under USB Type-C, which option is named as USB PD (the “PD” meaning “power delivery”), power delivery of up to 100 W is possible, facilitating rapid charging of a wide range of battery-powered devices from that single charger. Under this USB PD option, a given port may function as: (a) a “provider” or “source” of power, such as at a charger; or (b) a “consumer” or “sink” of power, such as at a battery that is being charged by the power provider. The host-device and source-sink relationships are not required to co-align between devices, such that a host for data and control purposes may be the device being charged (i.e., the sink for power purposes). Identification and negotiation of the source-sink relationship for power delivery under USB PD is performed by controller circuitry in each device at the USB-C port. More specifically, this controller circuitry detects the direction of current flow at the CC pins of the USB Type-C connector to identify the source-sink power transfer relationship of a USB-C connection. After the roles are identified, a higher power level than the default USB-C level (15 W) is then negotiated under USB PD by the source device “advertising” its output power capability by its coupling of a selected pull-up resistor or current source value at the CC pins; conversely, the sink detects its level of current consumption by coupling a pull-down resistor to the CC pins pin at its end, and monitoring the voltage drop.
Under the USB PD standard, a “fast role swap” (FRS) operation is also specified. The purpose of this operation is to limit the interruption of power delivery to a power consumer upon removal of a power source from the connection. FIGS. 1A and 1B illustrate an example of a situation in which an FRS occurs. In FIG. 1A, host device 2 is a USB PD capable host system, such as a smartphone, that is powered by its battery 3 when not receiving external power. In this example, host device 2 is in the role of a host, but it can also operate as an accessory (e.g., when connected to a desktop or laptop computer), and accordingly has a dual-role USB-C port (DRP). In this example, DRP 10 of host 2 is connected to a dual-role port of USB PD capable hub 4. Hub 4 is a conventional USB hub under the USB-C and USB PD standards, and includes a number of ports for coupling various devices together. In this example, hub 4 has a downstream-facing port (DFP) coupled to accessory 6, and an upstream-facing port (UFP) coupled to power source 8. Also, in this example, accessory 6 is a bus-powered accessory device, such as an external drive, projector, printer, or other conventional accessory. In at least one example, power source 8 is a wall charger.
The power connections and direction of power transfer among these devices on USB-C line VBUS are shown in FIG. 1A (the data connections are not shown). Essentially, the VBUS lines among the devices are connected together through hub 4, such that the VBUS pins at each of the various ports are at the same voltage, as negotiated by those ports. FIG. 1A illustrates in this example that power source 8 is providing power via hub 6 to host device 2 and accessory 6. The power provided by power source 8 is sufficient to charge battery 3 and provide operating power for the functions of host 2 and accessory 6. This power transfer arrangement is the result of detection and negotiation under USB PD as described above, resulting in a VBUS voltage that is above a certain specification limit (e.g., vSafe5V) under the USB-C standard.
FIG. 1B illustrates the same system as in FIG. 1A, but after the removal of power source 8. In response to removal of power source 8, the voltage at the VBUS line at hub 4 will drop below the specification limit, because no device is acting as a power source. According to the USB PD standard, hub 4 will detect this drop in voltage on the VBUS line and cause its DRP to issue a “fast role swap” (FRS) signal to the DRP at host device 2 over the non-grounded CC wire. The FRS signal is intended to cause DRP 10 at host 2 to quickly configure itself as a power source, rather than a power sink, so its battery can begin supplying power to accessory 6 via hub 4 with minimal interruption.
FIG. 1C illustrates the general architecture of a portion of DRP 10 of host device 2 in the arrangement of FIG. 1A, for purposes of its function in identifying and negotiating power transfer. This architecture corresponds generally to the TPS65982 USB Type-C and USB PD controller, power switch, and high speed multiplexer available from Texas Instruments Incorporated. As shown in FIG. 1B, USB-C/PD controller 12 includes programmable and custom logic circuitry connected to the CC1 and CC2 pins of the USB-C connector, at which controller 12 detects connection of a USB-C cable and the orientation of the connection (i.e., host-accessory and source-sink). Also, controller 12 manages the USB PD “contracts” (i.e., power source capability and demand by the power sink) and controls power switch transistors 14a, 14b accordingly. Power switch transistor 14a operates as a power switch connecting the VBUS line at the USB-C connector to a power line V_SRC in host device 2, and power switch transistor 14b similarly operates as a power switch for connecting the VBUS line to a power line V_SNK; gate signals SRC_EN and SNK_EN are driven by controller 12 to control power switch transistors 14a, 14b accordingly. In this simplified architecture, upon determining that its device 2 is a power sink, controller 12 will issue an active level on line SNK_EN to turn on power switch transistor 14b and an inactive level on line SRC_EN to turn off power switch transistor 14a, connecting the VBUS line at the USB-C connector to line V_SNK and isolating the VBUS line from line V_SRC. Conversely, in response to determining that its device 2 is a power source, controller 12 issues an active level on line SRC_EN to turn on power switch transistor 14a and an inactive level on line SNK_EN to turn off power switch transistor 14b, connecting line V_SRC in host device 2 to the VBUS line at the USB-C connector, and isolating line V_SNK from the VBUS line. Some conventional USB PD ports, such as those supported by the TPS65982 device, include power switching transistors that support bidirectional power transfer, both as a source and a sink. In any case, the DRP at host 2 will connect either a pull-down resistor or a pull-up resistor to the CC lines according to the appropriate orientation.
In the status shown in FIG. 1A, controller 12 of DRP port 10 in FIG. 1C is a power sink, with transistor 14b on and transistor 14a off to enable receipt of power from the VBUS line at line V_SNK. In an FRS event such as described above relative to FIG. 1B, host 4 will issue the FRS signal over the non-grounded one of the CC1 and CC2 wires. On receipt of that signal, controller 12 initiates its fast role swap process, which includes ensuring that the VBUS line at its USB-C connector is at a safe voltage at which transistors 14a, 14b can be switched without damage to the internal circuitry of host device 2. When that condition is detected, transistor 14b is turned off and transistor 14a is turned on, allowing the battery of host device 2 to source power to accessory 6 over the VBUS line.
Under the most recent USB PD standard (Universal Serial Bus Power Delivery Specification, Revision 3.0, V1.0a (March 2016), incorporated herein by reference), 150 μsec is the maximum time delay from an FRS indication for a DRP port to switch from a power sink orientation to a power source orientation and begin sourcing power. This aggressive limit necessitates a switching time for transistor 14a of less than 100 μsec. Such rapid switching of a large high-voltage transistor requires significant current capability for the driving circuitry, and can cause undesirably high levels of in-rush current.